[tabs name=”tabname1″ menu=”left”] [tab title=”Dipankar Pal”]

Dipankar Pal, Senior Member IEEE
Professor of Microelectronics in the Dept. of Electrical and Electronics Engineering, and Electronic Instrumentation in BITS-Pilani, Goa-Campus in India.

Effort Delay and Appropriate Optimizing Techniques

Accurate delay estimation and design of delay equalizers have of late become important in low-power, low-voltage processor design, optimization, multicore processors and signal processing applications such as delay equalized chains, wave pipe-lining, velocity selective recording of ENG and other biomedical signals. This is further significant because still most of the chain-of-delay blocks in analogue, mixed-mode and biomedical systems are pre-processed by manual designing prior to computerized/ digital post processing.
A chain of logic gates can be cleverly designed to realize delay accurately. Likewise optimum delay in circuits is observed to be realizable by appropriate selection of the topology and the device dimensions. The present endeavor is to analyze different types of delays – both topology dependent and topology independent and suggest optimum design methodology in a systematic study. The tutorial proposes to cover a wide range of circuit design examples where a systematic method can be used (instead of trial-and-error) to arrive at the best topology and transistor dimensions for optimum delay. The delay chain with branching shall also be taken into account through examples and the best topology and dimension for delay-optimization for network with branching shall also be proposed.

The topic and coverage has its genesis in the pioneering work on logical effort, electrical effort and branching effort in estimating effort delay by Ivan Sutherland et al, brought out in “Logical Effort: Designing Fast CMOS Circuits” Morgan-Kaufmann Publishers and studies by subsequent authors to this end. However appropriate circuit examples and techniques for solving design exercise with exceptions therein have been added to enrich the theory.

The tutorial shall be ideally targeting young researchers working on circuits for low power, low voltage processor, digital-core, mixed-mode, analogue and biomedical system designers. The participants need to have a background of digital electronics and digital VLSI design which is usually done in the first degree level in most universities of Asia, Australia, Europe and North America.

Short Biography

Born in 1961 in Chandannagar (a former French colony) in the state of West Bengal, in India Prof. Dipankar Pal had his early education there. He got 2nd rank in order of merit in his Board Examination in 1977; and received national scholarship (Govt. of India) which he continued to get throughout, till his graduation. After completing his Higher Secondary in 1979, he joined Indian Institute of Technology Delhi (IIT Delhi) and completed his graduation in Electrical Engineering in 1984. Prof. Pal received his PhD in electronics in 1997 from Jadavpur University, Calcutta, working in the area of analogue and mixed mode circuits and their digital control with tunability.
He did his post doctoral research in the University College London (2002, 2007-08) and University of Bath, UK (2003-05) where he worked on wet-electronics, analogue VLSI and ASIC with particular emphasis on current-mode circuits, biomedical and low power, low frequency applications.
Prof. Pal started his career in 1984 at the Central Research & Training Laboratories a unit of NCSM (under Ministry of Human Resource Development, Govt. of India) and was appointed Project Coordinator of Regional Science Centre, Bhopal from October 1990 till early part of 1998. Under his overall stewardship the Regional Science Cente, Bhopal was completed and inaugurated by the President of India in 1995. He left Central Research & Training Laboratories to join BIT Mesra as an Associate Professor in July 1998 where he became a Professor soon and headed the VLSI Research Group in the Department of Electronics & Communication Engineering during the period from 2006 to 2008. Prof. Pal became the Principal of Dr. B. C. Roy Engineering College, Durgapur and served there for about 3 years from 2008 and in mid-2011 he joined the Dhirubhai Ambani Institute of Information & Communication Technology, Gandhinagar, Gujarat, as Professor. He then became the Director of North Eastern Regional Institute of Science & Technology (NERIST) – a central university in north-eastern India on 24 October 2011 and served till 11 November 2014.
Presently he is a Professor of Microelectronics in the Dept. of Electrical and Electronics Engineering, and Electronic Instrumentation in BITS-Pilani, Goa-Campus in India.
Prof. Pal has guided a number of PhD’s and has over 50 publications in peer reviewed international and national journals and conferences. He was selected for UKIERI Fellowship (2007-08), EPSRC (UK) Post Doctoral Fellowship (2003-06), INSA-Royal Society (UK) Post Doctoral Fellowship (2002), SICI-DFAIT (Govt. of Canada) Faculty Research Fellowship (2000), Nehru-Trust for Cambridge University Small Studies & Research Grant (1997-98) and Nehru-Trust for Cambridge University Visiting Fellowship (1997-98).
He is a regular reviewer of IEEE Transactions on Circuits & Systems-I and II, IET Circuits, Devices and Systems and other reputed research journals.

[/tab] [tab title=”Rosdiadee Nordin”] Assoc. Prof. Ir. Dr. Rosdiadee Nordin
Universiti Kebangsaan Malaysia, Malaysia

Green Telecommunication: From Theory to Reality

Energy-efficient telecommunications, also known as green telecommunications is a dual-discipline research study, which involved combination between wireless telecommunication and renewable energy. The aim of this tutorial is to present state-of-the-art research in green mobile telecommunications and networking technology, start from the early years on fundamental research approaches until the practical deployment, which started to take place in today’s telecommunication industry. The research works in green communications are motivated by the needs to reduce the energy costs, reducing CO2 emissions and protecting the environment. Since the introduction of the first work in green communications, plenty of engineering approaches have been introduced in the past. Some of the techniques, such as cell-zooming, cell switch off/on, heterogeneous network, operator switch on/off and renewable energy system will be presented in this tutorial. This tutorial will balance between theoretical studies and practical applications with highlights on potential issues and challenges in green mobile networks. A case study, based on an intelligent base stations cooperation management with renewable energy system in a tropical climate country will be presented in this tutorial. Potential of green transmission techniques in next generation network, also known as Fifth Generation (5G) network will be highlighted at the end of the tutorial.
Importance & Timeliness

1. By the year 2020, mobile communication sector will be responsible for 51% of the total CO2 emissions from Information & Communication Technology (ICT) industry
2. Base stations contribute to 57% of the power consumption from the mobile network operator. This will increase the total CO2 emissions and operational expenditure (OPEX) in the long run.
3. Previously, the research focus on the green communications is limited to academic & research level. Recent studies show that there are several efforts to implement the green communication techniques in live mobile networks
4. Fifth Generation (5G) network is expected to roll out by 2020. Energy efficient is still become the main focus, with potential solutions for Massive-MIMO and small cells.
5. The solar radiation exposure in a tropical climate country is among the highest in the world. Thus, allow the use of solar energy as part of the solution for green telecommunication infrastructure.
6. To increase the awareness of the public and industry related to potential opportunities in green telecommunications


Short Biography

Rosdiadee Nordin received his Bachelor Degree in Electrical, Electronics and System Engineering from Universiti Kebangsaan Malaysia in 2001. After completed his five (5) years working experience with a telecommunication company, Maxis Communications, he decided to pursue for Ph.D. degree in Wireless Engineering at the University of Bristol, United Kingdom and finally completed his study in 2010. He is currently an associate professor in the Department of Electrical, Electronic and Systems Engineering at Universiti Kebangsaan Malaysia, a senior member of IEEE and a registered professional engineer in Malaysia. His research interests include green radio, TV White Space, cognitive radio, resource allocation and Fifth Generation (5G) wireless network.

[/tab] [tab title=”Sipra Das Bit”] Sipra Das Bit
Professor and former Head of the Department of Computer Science and Technology, Indian Institute of Engineering Science and Technology, Shibpur (formerly Bengal Engineering and Science University, Shibpur), West Bengal, India.

Post Disaster Situation Analysis using Delay Tolerant Network

The occurrence of catastrophic natural disaster disrupts all communication system, and it takes a lot of time to recover from that scenario. The scenario is more challenging in developing countries where very small population of people possesses smart expensive gadgets. This inspires us to work on exploring low-cost solutions for post-disaster crisis management. The proposed half-day tutorial will give a snapshot of the works undergoing towards conceptualization and implementation of such solutions for post disaster situation analysis and services.
Objectives and Motivation Modern days communication systems have been very popular in providing day-to-day services in our
life, but history has shown that in the event of disasters like Ayla in India, Katrina in USA, earthquake in Nepal and tsunami in Japan can severely impair all forms of communication, thus jeopardizing people’s lives. Alternatively, the occurrence of catastrophic natural disaster disrupts all communication system, and it takes a lot of time to recover from that scenario. The scenario is more challenging in developing countries where very small population of people possesses smart expensive gadgets.
Therefore, systematizing such chaotic situation through a series of cost effective technical innovations
in the area of wireless networking and its application is need of the day especially in developing country like India.
In view of the fact that people especially in disaster-prone area in India can’t afford to use smart and costly electronic gadget (e.g. water sensor that could differentiate between fresh, polluted and hazardous water used. in post-tsunami Japan), we have been motivated to work on exploring low-cost
solution for post-disaster crisis management. The proposed tutorial will give a snapshot of the works undergoing towards conceptualization and implementation of such solutions for post disaster situation analysis.

Short Biography
SIPRA DAS BIT is a Professor and former Head of the Department of Computer Science and Technology, Indian Institute of Engineering Science and Technology, Shibpur (formerly Bengal
Engineering and Science University, Shibpur), West Bengal, India. A recipient of the Career Award for Young Teachers from the All India Council of Technical Education (AICTE), she has more than 25 years of teaching and research experience.
Professor DasBit has published many research papers in reputed journals and refereed International conference proceedings. She also has two books and one book chapter on mobile computing to her credit. She is also principal investigator from her institute of a multi-institutional collaborative project on ‘Post-Disaster Situation Analysis and Resource Management Using Delay-Tolerant Peer-to-Peer Wireless Networks’ funded by ITRA, Media Lab Asia, Ministry of Communications and Information Technology, Government of India. Her current research interests include delay tolerant network, wireless sensor network and mobile computing.

[/tab] [tab title=”Vivek S. Deshpande”] Dr Vivek S. Deshpande

QoS and Design Challenges in Wireless Sensor Communications Networks

Now-a-days Wireless Sensor Networks plays predominant role in the communication domain. The data to be disseminated from multiple sources to the destination base station or sink is having vital significance. There are many problems with which data can be conveyed up to the sink. The congestion, reliability, delay, fairness, etc. are of main concern. These can be treated as Quality of Service parameters that govern the performance of the WSN. Above all the Energy s consumption is the main constrain for WSN node. It is very difficult to obtain good QoS by keeping energy consumption low. Even if response of one of QoS parameter will depends on the many other QoS parameters. We have to take care of all QoS parameters to improve the performance of the wireless sensor networks. This Quality of Services may improve the application base of the WSN. With the QoS parameters the data dissemination along with energy optimization is get affected. We have to check the performance of the WSN against the QoS metrics for different data inputs. This may contain the periodic- non periodic data, event based data, transient or burst data. For all these different types of inputs data we are checking the performance of QoS parameters like congestion, reliability and fairness. This may lead to new researcher to verify their results and excel their research work accordingly.

Short Biography

Dr Vivek Deshpande, Full Professor of Computer Engineering at Vishwakarma Institute of Technology under Pune University, India. He served as Associate Professor at MIT College of Engineering, Pune, India. He worked as Dean, Research and Head Information Technology Department from 2009 to 2011. Dr Vivek holds Bachelors and Masters Degree of Engineering in Electronics and Telecommunications from Pune University, India. He pursued his Doctorate from Nagpur University, India.
C urrently Dr Vivek keenly doing his research in Wireless Sensor Networks, Real Time Embedded Systems, High Performance Computer Networks and Cyber Physical Systems as well. He has 16 patents published on his name. He wrote 3 books/Chapters from well known publishers which are referred by many researchers who are working in related domain. His 23 years of teaching, Research and Industry experience is an asset to the organization. His expertise in the field of Wireless computer Networks and Distributed system helps in guidance to the UG, PG as well as PhD students. To cater the need of society, Dr Vivek now turns his research attention to Internet Of Things.
Dr Vivek is senior member of IEEE and currently working as Chair, IEEE Communication Society, Pune Chapter. He is also a member of Computer Society, India Council. Dr Vivek is currently an IEEE Executive Committee Member of Pune Section, India.

[/tab] [tab title=”Takayuki Ito et al”] Takayuki Ito, Ph.D., Prof. Nagoya Institute of Technology, Japan
Naoki Fukuta, Ph.D., Prof. Shizuoka University, Japan
Tokuro Matsuo, Ph.D., Prof. Advanced Institute of Industrial Technology, Japan
Katsuhide Fujita, Ph.D., Prof. Tokyo University of Agriculture and Technology, Japan

Social Value Engineering

Much attention has been focused on the collective intelligence of people worldwide. Interest continues to increase in online democratic discussions, which might become one of the next generation methods for open and public forums. To harness collective intelligence, incentives for participants are one critical factor. If we can incentivize participants to engage in stimulating and active discussions, the entire discussion will head in fruitful ways and avoid negative behaviors that encourage “flaming.” “Flaming” means a hostile and insulting interaction by Wikipedia. In our work, we developed an open web-based forum system called COLLAGREE that has facilitator support functions and deployed it for an internet-based town meeting in Nagoya as a city project for an actual town meeting of the Nagoya Next Generation Total City Planning for 2014-2018. Our experiment ran on the COLLAGREE system during a two-week period with nine expert facilitators from the Facilitators Association of Japan. The participants discussed four categories about their views of an ideal city. COLLAGREE registered 266 participants from whom it gathered 1,151 opinions, 3,072 visits, and 18,466 views. The total of 1,151 opinions greatly exceeded the 463 opinions obtained by previous real-world town meetings. We clarified the importance of a COLLAGREE-type internet based town meeting and a facilitator role, which is one mechanism that can manage inflammatory language and encourage positive discussions. While facilitators, who are one element of a hierarchical management, can be seen as a top-down approach to produce collective discussions, incentive can be seen as a bottom-up approach. In this talk, we also focus on incentives for participants and employ both incentives and facilitators to harness collective intelligence. I propose an incentive mechanism for large-scale collective discussions, where the discussion activities of each participant are rewarded based on their effectiveness. With these incentives, we encourage both the active and passive actions of participants. In this talk, I will present preliminary results with a large scale experiment with the Aichi-Prefecture local government in Japan.

Prof. Dr. Takayuki Ito
Head, Department of Techno-Business Administration, Department of Computer Science and Engineering, Graduate School of Engineering, Nagoya Institute of Technology, Japan
Dr. Takayuki ITO is Professor of Nagoya Institute of Technology. He received the B.E., M.E, and Doctor of Engineering from the Nagoya Institute of Technology in 1995, 1997, and 2000, respectively. From 1999 to 2001, he was a research fellow of the Japan Society for the Promotion of Science (JSPS). From 2000 to 2001, he was a visiting researcher at USC/ISI (University of Southern California/Information Sciences Institute). From April 2001 to March 2003, he was an associate professor of Japan Advanced Institute of Science and Technology (JAIST). From 2005 to 2006, he is a visiting researcher at Division of Engineering and Applied Science, Harvard University and a visiting researcher at the Center for Coordination Science, MIT Sloan School of Management. From 2008 to 2010, he was a visiting researcher at the Center for Collective Intelligence, MIT Sloan School of Management. He is a board member of IFAAMAS, Executive Committee Member of IEEE Computer Society Technical Committee on Intelligent Informatics, the PC-chair of AAMAS2013, PRIMA2009, General-Chair of PRIMA2014, and was a SPC/PC member in many top-level conferences (IJCAI, AAMAS, ECAI, AAAI, etc). He received the JSPS Prize, 2014, the Prize for Science and Technology (Research Category), The Commendation for Science and Technology by the Minister of Education, Culture, Sports, Science, and Technology, 2013, the Young Scientists’ Prize, The Commendation for Science and Technology by the Minister of Education, Culture, Sports, Science, and Technology, 2007, the Nagao Special Research Award of the Information Processing Society of Japan, 2007, the Best Paper Award of AAMAS2006, the 2005 Best Paper Award from Japan Society for Software Science and Technology, the Best Paper Award in the 66th annual conference of 66th Information Processing Society of Japan, and the Super Creator Award of 2004 IPA Exploratory Software Creation Projects. He is Principle Investigator of the Japan Cabinet Funding Program for Next Generation World-Leading Researchers (NEXT Program). Further, he has several companies, which are handling web-based systems and enterprise distributed systems. His main research interests include multi-agent systems, intelligent agents, group decision support systems, agent-mediated electronic commerce, and software engineering on offshoring.

Prof. Dr. Naoki Fukuta
Associate Professor in Computer Science at Shizuoka University, Japan.
Dr. Naoki Fukuta is an associate professor in Computer Science at Shizuoka University, Japan. He received his Doctor of Engineering from Nagoya Institute of Technology in 2002. In 2012, he received the IPSJ Yamashita SIG Research Award from the Information Processing Society of Japan, which is the largest society of computer science research in Japan. His main research interests include Semantic Web, Knowledge-based Software Engineering, Logic Programming, Mobile Agents, and Applications of Auction Mechanisms. His research is primarily rooted in autonomous, mobile, and multi-agent systems, and he has also developed several applications as well as their underlying programming environment. He served as a Deputy Chief Examiner (2011, 2012) and a Chief Examiner (2013) of Intelligent Systems Group, Journal of Information Processing. Since 2014, he is a senior member of IPSJ (Information Processing Society of Japan). He has organized or chaired several international conferences and workshops, including being the PC chair of 14th IEEE/ACIS International Conference on Computer and Information Science (ICIS2015) and a workshop co-chair of 10th International Conference on Knowledge, Information, and Creativity Support Systems (KICSS2015). He is a member of IEEE-CS (IEEE Computer Society), ACM (Association for Computing Machinery), JSAI (Japanese Society for Artificial Intelligence), IEICE (Institute of Electronics, Information, and Communication Engineers), JSSST (Japan Society of Software Science and Technology), and ISSJ (Information Systems Society of Japan).

Prof. Tokuro Matsuo, Ph.D.
Professor, Advanced Institute of Industrial Technology, Japan
Dr. Tokuro Matsuo is currently a full professor at Advanced Institute of Industrial Technology in Tokyo Metropolitan University from August 2012. Also, he is a Research Fellow of Software Engineering Information Technology Institute in Central Michigan University, USA; Founder of International Institute of Applied Informatics, Japan; Guest Professor at Bina Nusantara University, Indonesia; and a Research Project Professor at Nagoya Institute of Technology, Japan. He has some visiting appointments including Project Research Professor at Center for Green Computing in Nagoya Institute of Technology, Japan in 2011-2013; Visiting Researcher at University of California, Irvine, USA in 2010-2011; and Visiting Researcher at Shanghai University, China in 2010-2013. He received the Ph.D. from Dept. of Computer Science at Nagoya Institute of Technology in 2006. His current research interests include Electronic Commerce Mechanism Design, Artificial Intelligence, Applied Informatics, Material Informatics, Tourism Research, and Event and Convention Management Research. He is a member of AAAI and IEEE. He chaired international academic conferences over 40 events. He gave over 50 keynotes and invited talk at international conferences, symposia, and seminars. He also received over 40 awards and research grants from research foundations, company and Government.

Prof. Dr. Katsuhide Fujita
Faculty of Engineering, Tokyo University of Agriculture and Technology)
Dr. Katsuhide FUJITA is an Associate Professor of Faculty of Engineering, Tokyo University of Agriculture and Technology. He received the B.E., M.E, and Doctor of Engineering from the Nagoya Institute of Technology in 2008, 2010, and 2011, respectively. From 2010 to 2011, he was a research fellow of the Japan Society for the Promotion of Science (JSPS). From 2010 to 2011, he was a visiting researcher at MIT Sloan School of Management. From 2011 to 2012, he was a Project Researcher of School of Engineering, the University of Tokyo. His main research interests include multi-issue negotiation, multi-agent systems, decision support systems and text mining.

[/tab] [tab title=”SK Datta”] Soumya Kanti Datta
Research Engineer at Eurecom, France

Intelligence at the Edge: Using Fog Computing to Deliver Consumer Centric IoT Services

Internet of Things (IoT) is extending the Internet connection to physical things making them part of a
much larger platform, thereby requiring high computational capabilities for M2M data processing
and storage systems. Such demands will be generated by both fixed and mobile things covering a
wide geographic area and pertaining to heterogeneous domains and use cases. To meet these
demands, IoT platforms must have low latency, support for high degree of mobility and real time
data analysis with decision making abilities. From these requirements, cloud computing platform
may seem as the normal choice to deploy an IoT platform. Although the cloud platform provides
many benefits but also creates many challenges for latency sensitive and consumer centric IoT
services. For example, connected vehicle and intelligent transportation system services require low
latency as well as support for high mobility, real time data analytics and wide range of geographic
coverage. Fog computing can prove to be beneficial in these scenarios. Fog computing is a new
paradigm that extends the capabilities of cloud platform to the edge of the networks. Both
paradigms provide similar set services in terms of data storage, computation etc. But the “Fog” has
additional advantage due to its proximity to consumers, dense geographic coverage and mobility
support. Utilizing the Fog computing platforms, IoT applications and services could be operated from
intelligent end devices (e.g. access points, set top boxes, Road Side Units and M2M gateways) sitting
at the edge of the networks. This creates enormous intelligence at the edge and in turn reduces
latency, improves QoS and allows real time data analysis with actuation resulting in superior user
experience and creation of consumer centric IoT services. Additionally, Fog computing saves
bandwidth as data are process at the edge of network, promotes distributed architecture. Due to
dense geographic coverage and distributed operations, “Fog” promotes fault tolerance, reliability
and maintains scalability of the system.
The tutorial will cover architectural issues, network challenges, service enablement and service
management for Fog Computing driven consumer centric IoT. It will also discuss underlying
technologies for Fog enablement, prototyping experiences and activities in various standard
development organizations. These aspects are highly related to the theme of IEEE Globecom 2016.
Thus, the tutorial will augment the knowledge of the audience and foster a great discussion with
them as well as exchanging ideas and share new findings. The outline of the tutorial consists of
topics which are considered as hot topics for both academia and industry. The tutorial scope is also
timely. The tutorial is expected to attract a large audience comprising of academia, industry,
engineers, standard developers and other stakeholders in IoT and Fog Computing.

Short Bio
Soumya Kanti Datta is a research engineer in EURECOM, France and is working on French research
projects “Smart 4G Tablet”, “WL-Box 4G” and “DataTweet”. He has also co-founded a start-up
company focusing on IoT based products for smart cities and wearable devices. His research focuses
on innovation, development of next-generation technologies and standardization in Internet of
Things, Machine-to-Machine Communication, Mobile Edge Computing, Mobile Apps and Computer
Security. He is an active member of IEEE Consumer Electronics Society and IEEE Communication
Society. He has published more than 35 research papers in top IEEE Conferences and Journals.
Soumya has served as a Track Chair of ICCE 2015 and ICCE 2016, the flagship conference of IEEE CE
Society and has organized and co-chaired several special sessions on IoT in IEEE conferences. He is
also serving as TPC member and designated reviewer for several IEEE conferences. He is a frequent
participant of ETSI events and regularly gives tutorials and presentations on IoT at various events
including ETSI and IEEE conferences. Currently Soumya is involved in oneM2M standards and W3C
Web of Things Interest Group where he is leading the task force on “Discovery and Provisioning” and
actively contributing to their standard development activities.

[/tab] [tab title=”Agung Trisetyarso”] Agung Trisetyarso,IEEE Member
Faculty Member in the Department of Computer Science, Universitas Bina Nusantara
Fithra Faisal Hastiadi
Faculty Member in the Faculty of Economics and Business, Universitas Indonesia

Harnessing Disruptive Innovations Dynamics: Dirac-Solow-Swan Model Approach

Harnessing disruptive innovations dynamics is theoretically presented based on Dirac-Solow-Swan model. The quantum view leads into the conclusion that hyperfine splitting of capital is occurred due to the disruption and as a consequence is the excitation of capital and labour from the old into the new industry of disruption. The bifurcation of capital dynamics occurs due to Christensen effect, after market symmetry breaking. It is shown that harnessing disruptive innovations relies on controlling expansion factor of capital accumulation on mainstream market. The implementation of the proposal in the recent issues will be discussed.

Topics and coverage on the two folds:
1. Strategic and policy: Recent Indonesian government policy, Indonesian economic forecasting, and the future of innovation in Indonesia.
2. Theoretical foundations: Mathematical model of disruptive innovations such as Dirac equation, Solow-Swan model, and Dirac Bracket.

Short Bio
Agung Trisetyarso is a Faculty Member at Department of Computer Science, Doctoral Programme, Bina Nusantara University (2015-present) and was a Faculty Member at Department of Informatics, Telkom University (2011-2015). He was awarded Bachelor of Science (Thesis: “Application of Darboux Transformation to solve Multisoliton Solution on Non-linear Schroedinger Equation”; Supervisor: Alexander Iskandar, Ph.D) and Master of Science from Department of Physics, Institut Teknologi Bandung. His Ph.D (September 2007 – April 2011) was obtained from Applied Physics and Physico-Informatics at Keio University, in the field of Quantum Information and Computation (Thesis: “Theoretical study towards realization of measurement-based quantum computers”) under supervision of Prof. Kohei M. Itoh and Prof. Rodney Van Meter.
He is actively to give presentations in various seminars, workshops, and conferences such at IEEE, ICTP (2010, 2012), Workshop of Quantum Repeaters and Networks, Duke University (2015), visiting professor at Chitkara University (2013), India, and visiting at Isaac Newton Institute, University of Cambridge (2013, 2014) and DAMTP Cambridge (2016).

Fithra Faisal Hastiadi obtained his BA in Economics from the University of Indonesia. During his BA, he worked as a teaching assistant in the University of Indonesia at the Department of Economics before he continued his study to Keio University, Japan, from where he got his MA degree. He then earned his PhD degree from Waseda University, Japan. He has published a number of articles for reputable journals and working papers. He shares a significant contribution for ASEAN 2030 study while he was working as a research associate at Asian Development Bank Institute (ADBI) in Tokyo back in 2011. He also served as a senior researcher at the National Economic Council where he gives advices for the President of Indonesia from 2012 to 2013. Currently he is serving as Research and Community Engagement Manager at Faculty of Economics University of Indonesia.
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